Enhanced accessibility to FPGAs for hardware acceleration in edge compute systems

Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families that considerably enhances productivity and ease of design by enabling C++ algorithms to be directly translated to FPGA-optimised RTL code.

“SmartHLS enhances our Libero SoC design tool suite and makes the vast benefits of our award-winning mid-range PolarFire and PolarFire SoC platforms accessible to a diverse community of algorithm developers without them having to become FPGA hardware experts,” said Bruce Weyer, vice president of Microchip’s FPGA business unit. “Together with our VectorBlox Neural Network Software Development Kit, these tools will greatly improve designers’ productivity in creating cutting-edge solutions using C/C++ based algorithms for applications such as embedded vision, machine learning, motor control and industrial automation using FPGA-based hardware accelerators.”

Based on the open-source Eclipse integrated development environment, the design suite employs C++ software code to generate an HDL IP component for integration into its Libero SmartDesign projects. This allows engineers to describe hardware behaviour at a higher level of abstraction than is possible with traditional FPGA RTL tools.

It improves productivity while decreasing development time through a multi-threading API that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism compared to other HLS offerings.

The SmartHLS tool needs up to 10 times fewer lines of code than an equivalent RTL design, with the resultant code being easier to read, understand, test, debug and verify. The tool also simplifies exploration of hardware microarchitecture design trade-offs and enables a developer’s pre-existing C++ software implementations to now be used with PolarFire FPGAs and FPGA SoCs.

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