Power Design Tip 46: Properly Synchronizing Buck FET Timing

Timing optimization is becoming increasingly important as engineers strive to achieve the highest efficiency possible from their power supplies. During switching, there are two transition phases: low side switch on and high side switch on.

Turning on the switch on the low side is critical because there is little loss in this transition phase, ie “lossless turn-on”. After the high-side switch is turned off, the Inductor current drives the switch node voltage to ground without damage. The best time to turn on the low side switch is at the end of the transition. If the body diode conducts briefly before the low side turns on, it doesn’t matter because it doesn’t cause reverse recovery losses. The excess current carrying at this junction is fully dissipated before the next switching transition. However, if the current remains in the body diode for a long time, there will be excessive conduction losses. The high-side FET turn-on timing is the most important transition. Turning on too early results in shoot-through losses due to cross conduction with the low-side FET; turning on too late results in higher conduction losses and excess current-carrying injection into the low-side FET body diode (which must be recovered). In either case, efficiency will be reduced.

To illustrate the relationship between efficiency and timing of the drive signal, I built some power supplies with adjustable delay of the drive signal. After that, I compared the efficiency and the delay time and studied the relationship between them.picture1A-1C Results are shown.

picture1A The situation is shown when the high-side FET is turned on before the low-side FET is fully turned off. There is a significantly larger Miller region in the low-side gate drive, where the low-side and high-side FETs are turned on at the same time, resulting in shoot-through current in the power stage. When the low-side FET finally turns off, there is additional voltage overshoot at the switch node.existpicture1BIn , the high-side FET turns on after the low-side FET turns off and current has developed in the body diode. When the high-side FET turns on, it restores the body diode and there is a current spike that causes the switch node voltage to ring. However, this phenomenon is not significant due to the extremely short reverse recovery time (12nS) of the body diode of the MOSFET used. The slower the body diode, the more pronounced the ringing.picture1C Has the highest power efficiency. The low-side gate voltage drops near ground before the high-side switch is turned on. The high side turns on before the lower body diode conducts, minimizing switch node ringing.

Power Design Tip 46: Properly Synchronizing Buck FET Timing

picture1A Advanced high-side timing generates shoot-through current

Power Design Tip 46: Properly Synchronizing Buck FET Timing

picture1B Body diode conducts during high side drive delay

Power Design Tip 46: Properly Synchronizing Buck FET Timing

picture1C Optimal Timing for Higher Efficiency and Lower Stress

picture2 Efficiency curves for a 12V to 1V/15A, 300kHz power stage are shown for different gate drive timings. The left side of the scale indicates that the high-voltage side switch is turned on in advance,As shown1A shown. The right side represents a delayed high-side gate drive (picture1B). On the left, efficiency drops sharply due to shoot-through current losses in the power stage. On the right, the efficiency gradually decreases.

There are two reasons for the gradual decline in efficiency: conduction losses from the body diode of the low-side FET and reverse recovery losses. During the body diode conduction period, the body diode voltage drops by about 0.7 volts.equation1 represents the maximum power efficiency during the conduction period of the body diode, which is approximately as follows:

Power Design Tip 46: Properly Synchronizing Buck FET Timing (1)

If the body diode conducts for 50ns in 3us, it can have about 1.2% effect on the overall efficiency. For this power stage, reverse recovery losses are negligible due to the use of MOSFETs with a short reverse recovery time of 12nS.

picture2 Driver timing can greatly affect efficiency

In conclusion, proper gate drive signal timing in a synchronous buck regulator is critical to maximize efficiency. This timing minimizes the low-side FET body diode conduction time. Turning on the high-side FET is the most critical transition phase, and avoiding turning on the high-side FET until the low-side is fully turned off. Doing so minimizes switching losses and reduces voltage ringing during transitions.

For more details, see the April 2003 TI Application Note (SLUA281) article “Gate Drive Boost Synchronous DC/DC Power Converter Efficiency Prediction

For more details on this article and other power solutions, please visit:http://www.ti.com.cn/lsds/ti_en/analog/powermanagement/power_portal.page.

The Links:   104PWBJ1-C LM190E08-TLJ2 IGBTMODULE

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 3.0 Unported License.
Permalink: https://mitigbt.com/power-design-tip-46-properly-synchronizing-buck-fet-timing/
Tags:
« »